A Hardware Spinal Decoder

Peter Iannucci, Kermin Elliott Fleming, Jonathan Perry, Hari Balakrishnan, Devavrat Shah
ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS), Austin, TX, October 2012

Spinal codes are a recently proposed capacity-achieving rateless code. While hardware encoding of spinal codes is straightforward, the design of an efficient, high-speed hardware decoder poses significant challenges. We present the first such decoder. By relaxing data dependencies inherent in the classic M-algorithm decoder, we obtain area and throughput competitive with 3GPP turbo codes as well as greatly reduced latency and complexity. The enabling architectural feature is a novel "alphabeta" incremental approximate selection algorithm. We also present a method for obtaining hints which anticipate successful or failed decoding, permitting early termination and/or feedback-driven adaptation of the decoding parameters.

We have validated our implementation in FPGA with on-air testing. Provisional hardware synthesis suggests that a near-capacity implementation of spinal codes can achieve a throughput of 12.5 Mbps in a 65 nm technology while using substantially less area than competitive 3GPP turbo code implementations.

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Bibtex Entry:

@inproceedings{iannucci2012hardware,
   author =       "Peter Iannucci and Kermin Elliott Fleming and Jonathan Perry and Hari Balakrishnan and Devavrat Shah",
   title =        "{A Hardware Spinal Decoder}",
   booktitle =    {ACM/IEEE Symposium on Architectures for Networking and Communications Systems (ANCS)},
   year =         {2012},
   month =        {October},
   address =      {Austin, TX}
}